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description the bus-65153 is a complete, dual redundant mil-std-1553b remote terminal. packaged in a 1.9" x 1.0" x 0.2", 70-pin ceramic package, the bus-65153 provides the transmitter voltage level required by mil-std- 1760. also in support of mil-std- 1760, the rt address inputs are latchable. the bus-65153 contains two low power transceivers and a ddc custom designed chip. this chip includes dual encoder/decoder, rt protocol logic, tri- state data buffers, and dma transfer con- trol logic. the bus-65153 supports all 13 dual redundant mode codes, any combi- nation of which may be illegalized by an external prom, pld, or ram device. parallel data transfers are accomplished via a dma type interface. both 8-bit and 16-bit transfers are supported. the bus-65153 can be easily inter- faced to most cpu's. in addition, the bus-65153 can interface directly to minimum complexity subsystems such as switches, d/a converters, etc. the address bus and transfer control sig- nals may be configured for either two-state or three-state operation. use of the three- state address mode reduces the number of external components required for a dma processor interface. the input clock frequency is user selectable for either 12 or 16 mhz. in the 12 mhz mode, the decoder operates at 24 mhz, providing superior word error rate and zero crossing distortion tolerance. the busy, service request, and subsystem flag rt status word bits are provided as discrete pins, allowing for easy access by the subsystem. various message timing and error flag indicators are provided to facili- tate the subsystem interface. mil-std-1553b, notice 2 and mil-std-1760b small terminal interface circuit stic * upper data bus data bus upper data buffer d15-d8 db_sel bus-25679 8 7 1 tx/rx a 55 ohms a d i r a x f 55 ohms 55 ohms bus a bus b tx_inh transmitter inhibit a x f a d i r b d i r b x f b x f b d i r bus-25679 5 4 8 7 5 4 1 3 3 tx/rx a tx/rx b tx/rx b 1553 bus i/o 2 2 transceiver a transceiver b encoder/ decoder and watchdog timer dma handshake control logic and transfer dt_req dt_grt dt_ack hs_fail cs wrt width select dma handshake data transfer control address 14-bit address bus lower data bus tri-state control a13-a0 lower data buffer d7-d0 addr_ena address buffers registers 5 r.t. address parity and compare logic 55 ohms clk clk_sel rt_ad4-rt_ad0 rt_ad_p rt_ad_err r . t. clock input and frequency select rt_ad_lat address reset ssflag busy illegalization and status inputs illcmd service_request reset and transmitter inhibit logic status, illegalization, last command, status, current command, and bit word r.t. state and machine logic nbgrt incmd gbr me rt_fail message timing signals * ? 1991, 1999 data device corporation figure 1. bus-65153 block diagram features ? supports mil-std-1553b notice 2 and mil-std-1760 stores management ? complete integrated remote terminal including: - dual low-power transceiver - complete rt protocol logic ? small, 70-pin ceramic package ? meets 1553a/mcair response time requirements ? selectable 8/16-bit dma interface ? optional tri-state address bus and transfer control signals ? direct interface to simple systems ? selectable input clock, 12 or 16 mhz ? mil-prf-38534 processing available note: transformers are external bus-65153
2 table 1. bus-65153 specifications parameter min max - 0.3 - 0.5 + 0.3 + 0.3 - 0.5 11 0.500 k w pf v p - p v peak 6 20 18 -250 100 22 21 150 9 27 27 10 250 300 0.8 20 20 0.4 0.5 3.4 4.5 4.5 -15.75 4.5 4.5 -12.6 5 65 20 55 90 160 5.5 5.5 -14.25 5.5 5.5 -11.4 115 50 112 175 300 v v v v v v ma ma ma ma ma absolute maximun ratings supply voltage n logic + 5v transceiver + 5 v n - 15 v n - 12 v logic n voltage input range v v v v v typ units logic v ih v il i ih (v in =v cc ) i il (v in =gnd) v oh (i oh = 0) v oh (i oh = max) v ol (i ol = 0) v ol (i ol = min) i ol i oh receiver differential input resistance n (bus-65153, bus-65163, bus- 65154, bus-65164) (notes 1 - 6) differential input capacitance n (bus-65153, bus-65163, bus-65154, bus-65164) (notes 1 - 6) threshold voltage, transformer coupled, measured on stub common mode voltage (note 7) v p - p v p - p v p - p mv p - p , diff mv nsec table 1. bus-65153 specifications parameter min typ power supply requirements (continued) current drain (bus-65154, bus-65164, note 9) n + 5 v logic (ch a, ch b) n - 12 v (ch a, ch b) idle 25% duty cycle 50% duty cycle 100% duty cycle 65 30 87 135 230 115 60 120 185 305 ma ma ma ma ma power dissipation bus-65153, bus-65163 n total hybrid idle 25% duty cycle 50% duty cycle 100% duty cycle n hottest die idle 25% duty cycle 50% duty cycle 100% duty cycle bus-65154, bus-65164 n total hybrid idle 25% duty cycle 50% duty cycle 100% duty cycle n hottest die idle 25% duty cycle 50% duty cycle 100% duty cycle 0.625 0.850 1.075 1.525 0.335 0.600 0.860 1.385 0.685 0.985 1.285 1.885 0.290 0.590 0.890 1.490 1.325 1.963 2.600 3.875 0.68 1.06 1.45 2.23 1.295 1.727 2.160 3.035 0.59 0.92 1.36 2.16 w w w w w w w w w w w w w w w w 16.0 12.0 33 40 0.01 0.1 0.001 0.01 67 60 mhz mhz % % % % % % thermal thermal resistance, junction-to- case, hottest die ( q jc) n bus-65153, bus-65163 n bus-65154, bus-65164 operating junction temperature storage temperature lead temperature (soldering for 10 seconds) 1553 message timing rt response time 16 mhz 12 mhz rt-to-rt no response timeout (note 8) transmitter watchdog timeout -55 -65 6.00 6.18 18.25 6.5 6.5 18.9 668 160 150 +300 6.96 6.76 19.5 c/w c/w c c c m s m s m s m s clock input frequency n nominal value (selectavle) clocksel input = logic 0 clocksel input = logic 1 n long term tolerance 1553a compliance 1553b compliance n short term tolerance, 1 second 1553a compliance 1553b compliance duty cycle 16 mhz 12 mhz 5.54 5.54 units max power supply requirements voltages/tolerances (bus-65153, bus-65163) n + 5 v (logic) n + 5 v (ch a, ch b) n - 15 v (ch a, ch b) voltages/tolerances (bus-65154, bus-65164) n + 5 v (logic) n + 5 v (ch a, ch b) n - 12 v (ch a, ch b) current drain (bus-65153, bus-65163, note 9) n + 5 v logic (ch a, ch b) n - 15 v (ch a, ch b) idle 25% duty cycle 50% duty cycle 100% duty cycle transmitter differential output voltage n direct coupled accross 35 ohms, measured on bus n direct coupled accross 70 ohms measured on stub bus-65153, bus-65163 (note 10) bus-65154, bus-65164 output noise, differential (direct coupled) output offset voltage, tran sformer coupled accross 70 ohms rise/fall time 2.0 -20 -20 vcc+0.4 3.7 -3.4 10 0.860 10 7.0 7.0 - 18.0 - 18.0 vcc+0.5 v v ma ma v v v v ma ma
introduction general the bus-65153 is a complete mil-std-1553 remote terminal (rt) bus interface unit. contained in the hybrid are a dual trape- zoidal transceiver and manchester ii encoder/decoder, and remote terminal (rt) protocol logic for mil-std-1553b. also included are built-in self-test capability and a parallel subsystem interface. the subsystem interface includes a 14-bit address bus and a data bus that may be configured for either 8-bit or 16-bit dma transfers. the transceiver front end of the bus-65153 is implemented by means of low-power bipolar analog monolithic and thick-film hybrid technology. the transceiver requires +5 v and -15 v only (no +15 v is required) and includes voltage source transmitters. the voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. in addition, the monolithic transceivers provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, mak- ing the bus-65153 suitable for mil-std-1760 applications. the receiver sections of the bus-65153 are fully compliant with mil-std-1553b in terms of front end overvoltage protection, threshold and bit-error rate. the bus-65153 implements all mil-std-1553 message for- mats, including all 13 of the 1553b dual redundant mode codes. any subset of the possible 1553 commands (broadcast, t/r bit, subaddress, word count/mode code) may be optionally illegal- ized by means of an external prom, pal, or ram device. an extensive amount of message validation is performed for each message received. each word received is validated for correct sync type and sync encoding, manchester ii encoding, parity, and bit count. all messages are verified to contain a legal, defined command word and correct word count. if the bus- 65153 is the receiving rt in an rt-to-rt transfer, it verifies that the t/r bit of the transmit command word is a one and that the transmitting rt responds in time and contains the correct rt address in its status word. the 65153 may be operated from either a 12 mhz or 16 mhz clock input. in the 12 mhz mode, the decoder samples incoming data with both edges of the clock input. this, in effect, provides for 24 mhz decoder sampling. benefits of the higher sampling rate include a wider tolerance for zero-crossing distortion and improved bit error rate performance. the bus-65153 includes a hardwired r.t. address input. this includes 5 address lines, an address parity input, and an address parity error output. the rt address can also be latched internally by means of the address latching input signal rt_add_lat. the 65153 supports command illegalization. commands may be illegalized by asserting the output signal illcmd low approximately 5 ms after the mid-parity bit zero- crossing of the received command word. command words may be illegalized as a function of broadcast, t/r bit, subaddress, word count and/or mode code. an internal built-in-test (bit) word register is updated at the end of each message. the contents of the bit word register are transmitted in response to a transmit bit word mode command. the bus-65153 provides a number of real-time out- put signals. these various signals provide indications of mes- sage start, message in progress, valid received message, mes- sage error, handshake fail, and looptest fail or transmitter time- out. the bus-65153 may be used in a wide variety of interface con- figurations. the 65153 has an 8/16-bit tri-state data bus and an address/control bus that may be pin programmed for either two- state or three-state operation. the three-state mode allows the bus-65153 to be connected directly to the host processor's data, address, and control buses in a dma configuration. the bus-65153 includes standard dma handshake signals (request, grant, and acknowledge) as well as transfer control outputs (cs and wrt). the dma interface may operate in either a 16-bit or 8-bit mode, supporting both word-wide and byte-wide transfers. the dma interface also allows the 65153 to be interfaced direct- ly to a simple system that doesn't have a microprocessor. this provides a low-cost 1553 interface for a/d and d/a converters, switch closures, and actuators. the bus-65153 may also be used in a shared ram interface configuration. by means of tri-state buffers and a very small amount of glue logic, the 65153 will store command words and access data words to/from dedicated mailbox areas in a 3 in (mm) oz (gm) 0.6 (17) units max typ min parameter table 1. bus-65153 specifications 1.9 x 1.0 x 0.215 48.26 x 25.4 x 5.46 physical characteristics size n 70-pin, dip, flat pack weight n 70-pin, dip, flat pack notes: notes 1 through 6 are applicable to the receiver differential resistance and differential capacitance specifications: (1) specifications include both transmitter and receiver (tied together internally). (2) measurement of impedance is directly between pins tx/rx a(b) and tx/rx a(b) of the bus-65153 or bus-65163 hybrid. (3) assuming the connection of all power and ground inputs to the hybrid. (4) the specifications are applicable for both unpowered and powered conditions. (5) the specifications assume a 2 volt rms balanced, differential, sinu- soidal input. the applicable frequency range is 75 khz to 1 mhz. (6) minimum resistance and maximum capacitance parameters are guaranteed,but not tested, over the operating range. (7) assumes a common mode voltage within the frequency range of dc to 2 mhz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), referenced to hybrid ground. use a ddc recommended transformer or other transformer that provides an equivalent minimum cmrr. (8) rt-to-rt timeout is measured from the mid-parity crossing of the transmit command word to the mid-sync crossing of the transmitting rt status word. (9) current drain is for total hybrid (e.g., +5v supply current includes the sum of logic +5v supply current, channel a +5v supply current and channel b +5v supply current). transmitting duty cycles assume one channel transmitting and alternate channel idle. (10) compliant with 1760 applications.
shared ram for each broadcast / t-r bit / subaddress / mode code. if a more elaborate shared ram interface is needed, the bus- 65153 may be interfaced to a bus-66315 memory management unit. if a bus-66315 is used, the address bus of the bus-65153 is not used for accessing the system ram (although the address outputs may still be used for command illegalizing). the bus-66315 provides an rt lookup table, allowing the mapping of the various t-r/subaddresses to user programmable areas in the bus-66315's 64k x 16 shared ram address space. the bus-66315 also provides a stack area of ram. the stack provides a chronology of all messages processed, storing a block status word (message channel, completion, and validity information), an optional time tag word and the received command word for each message processed. the bus-66315 also provides maskable interrupts to the host processor for end- of-message and/or message error conditions. address mapping the memory allocation scheme for the bus-65153 14-bit address bus is defined as follows: a13: broadcast/ownaddress a12: transmit/receive a11-a7: subaddress 4-0 a6: data/command a5-a1: word count/current word count a0: upper/lower byte (8-bit mode only) the method of address mapping implemented by the bus- 65153 provides for a mailbox allocation scheme for the storage of command and data words. the address outputs a13 through a1 map directly into 8k words (16k bytes) of processor address space. a0 is used for upper/lower byte selection in the 8-bit dma mode. the same address map is applicable for both the dma and shared ram (without the bus-66315) interface configura- tions. the bus-65153's addressing scheme maps messages in terms of broadcast/own address, transmit/receive, subaddress, and mode code. a 64-word message block is allocated for each t/r-subaddress. the received command word for all nonmode code messages is stored at relative word location zero (0) within the respective message block. for mode code messages, the address for the received command word is offset from location zero (0) within the message block for subaddress 0 or 31. the value of the address offset is equal to the mode code field of the respective command word (0 to 31). for nonmode code messages, the data words to be transmitted or received are accessed from (to) relative locations 32 through 63 within the message block. for mode code messages with a single data word that is not read from internal register, the address for the data word is offest from location 32 within the 64-word message block for subaddresses 0 and 31. the value of the address offset is equal to the mode code field of the received command word. the data words transmitted in response to transmit last command or transmit bit word mode commands are accessed from a pair of internal registers. dma interface an 8/16-bit data bus, a 14-bit address bus, and six control sig- nals are provided to facilitate communication with the parallel subsystem. the control signals include the standard dma hand- shake signals dt_req, dt_grt, dt_ack as well as the trans- fer control outputs cs and wrt. hs_fail provides an indication to the subsystem of a handshake failure condition. data is transferred between the subsystem and the bus-65153 via a dma handshake, initiated by the bus-65153. a read operation is defined to be the transfer of data from the subsys- tem to the bus-65153. conversely, a write operation transfers data from the bus-65153 to the subsystem. if the bus-65153 is in 16-bit mode, data is transferred as a sin- gle 16-bit word. in 8-bit mode, data is transferred in a pair of byte transfers within the same dma handshake cycle. the upper byte is transferred first with a0=1, followed by the lower byte with a0=0. handshake fail if the bus-65153 (stic) asserts dt_req and the subsystem does not respond with dt_grt in time for the bus-65153 to complete the word transfer, the hs_fail output will be asserted low to inform the subsystem of the handshake failure and bit d12 in the internal built-in-test (bit) word is set to logic ?1." if the handshake failure occurs on a data word read transfer (transmit command) the stic will abort the current message processing and not transmit erroneous data back to the bus controller. in the case of a handshake failure on a write transfer (receive com- mand word transfer, transmit command transfer, or a receive data word transfer) the stic will set the handshake failure out- put and bit word bit, and continue processing the current mes- sage. dma read operation whenever the bus-65153 needs to read a word from the sub- system, it asserts the signal dt_req low. if the subsystem asserts dt_grt in time, the bus-65153 will then assert a13 through a1 (and a0 for the 8-bit mode), wrt high, along with dt_ack and cs low to enable data from the subsystem. after the transfer of each data word has been completed, address bus outputs a5 through a1 are incremented. this pro- vides the option of connecting the bus-65153 address lines directly to the host processor's address bus to access the sub- system ram, if desired. dma write operation whenever the bus-65153 needs to transfer data to the subsys- tem, it initiates a dma write cycle. the bus-65153 asserts dt_req. the subsystem must respond with dt_grt. if dt_grt was received in time, the bus-65153 will then assert dt_ack. the bus-65153 will then assert a13 through a1 (and 4
4kx1 prom a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 sa 2 wc 0 wc 1 wc 2 wc 3 sa 3 sa 4 wc 4 sa 0 sa 1 a07 a10 a11 a08 a09 a01 a02 a03 a04 a05 bus-65153 "stic" a12 a13 illegal a10 a11 oe bro t/r d0 clock 1 2 3 incmd clock in oscillator q q d a0 in 8-bit mode) and wrt low, followed by cs low. the sub- system may then use the rising edge of cs to latch the data. similar to the dma read operation, the address outputs a5 through a1 are incremented after the completion of a dma write operation. message processing operation following the receipt and transfer of a valid command word, the bus-65153 will attempt to (1) transfer received 1553 data to the- subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly built-in-test) information to 1553, and/or (4) set status conditions. the bus-65153 responds to all nonbroadcast messages with a 1553 status word. rt address rt address (rt_ad 4-0, (rt_ad4 = msb)) and rt address parity (rt_ad_p) should be programmed for a unique rt address and reflect an odd parity sum. the bus-65153 will not respond to any mil-std-1553 commands or transfer received data from any nonbroadcast messages if an odd parity sum is not presented by rt_ad4-0 and rt_ad_p. an address parity error will be indicated by a low output on the rt_ad_err pin. the input signal rt_ad_lat operates a transparent latch for rtad4-rtad0 and rtadp. if rt_ad_lat is low the output of the latch tracks the value presented to the input pins. if rt_ad_lat is high, the output of the internal latch becomes latched at the values presented when rt_ad_lat was low. command illegalization the bus-65153 provides for command illegalization. if a com- mand is illegalized, the bus-65153 will set the message error bit and transmit its status word to the bus controller. no data words will be transmitted in response to an illegalized transmit command. data words associated with an illegalized receive command will, however, be presented to the subsystem. illcmd is sampled approximately 5 ms following the mid-parity bit zero crossing of the received command word (reference figures 4-9). command illegalization can be implemented using either a two-state or three-state address bus. an external prom, pld, or ram device can be used to define the legality of specific commands. any subset of the possible 1553 commands can be illegalized as a function of broadcast, t/r bit, subad- dress, word count, and/or mode code. illegalizing commands in the two-state mode, based on broad- cast, t/r bit, subaddress, and/or mode code, may be done by means of a programmable device such as a prom. the address outputs from the stic may be connected directly to the address inputs to a prom. illegalizing commands in the two- 5 figure 2. bus-65153 two-state illegalization
6 d00 d01 wc 0 wc 1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 4kx1 prom sa 2 wc 2 wc 3 sa 3 sa 4 t/r wc 4 sa 0 sa 1 a07 a10 a11 a08 a09 a12 d02 d03 d04 bus-65153 "stic" a13 illegal _ _ _ _ _ _ _ bro a11 oe _ _ d0 cs _ _ q d q state mode, based on broadcast, t/r bit, subaddress, and word count requires an external latch to store the value of the word count field. the word count must be latched after the address lines a5...a1 are updated for the present command and before these address lines are cleared to 00000 for the command word transfer. the word count address lines (a5...a1) are multiplexed internal- ly between the latched word count field of the command word, and the current word counter. while the signal incmd is high (logic 1) these address lines reflect the word count field of the present command. while incmd is low (logic 0) these signals represent the value of the current word counter, which is cleared to zero at the start of a message, and is incremented after each data word transfer. the output of the illegalization prom may be latched using a flip-flop and an and gate (see figure 2). the output signal incmd from the stic is used as the clock enable input to the flip-flop. the flip-flop is updated on every rising clock edge while incmd is high, and is not updated while incmd is low. this allows the output of the prom to be updated on the last clock edge before incmd is asserted low. once incmd is asserted, the clock enable input to the flip-flop is removed, thus preserving the value of the latched illegal bit. illegalizing commands in the three-state mode of operation also requires the use of a latch. the latch must be updated during a word transfer since the address lines are normally in a high impedance state. figure 3 illustrates a method of latching the output from the prom using a flip-flop and the signal cs. the signal cs is driven low during every word transfer. the only word transfer that takes place before the illegal command input (illcmd) input is sampled is the command word transfer. the word count field of the command word may be obtained directly from the lower 5 bits of the data bus. the subaddress, t/r, and broadcast signals are available on address lines a07-a13. note that the signal cs will be asserted twice during a transfer in the 8-bit mode of operation. the word count field is located in the lower byte, which is presented during the second byte transfer. the second cs will, therefore, latch the appropriate value for illegal. figure 3. bus-65153 three-state illegalization
this method of latching the address lines places a constraint on the access time of the prom and on the maximum request to grant time for the command word transfer. the access time of the prom must be less than 195 ns. if the data bus grant signal is held off too long, the illcmd input will not be updated in time. the maximum request to grant time is equal to the following: transfer type tmax 16-bit @12 mhz 2.455 ms 16-bit @16 mhz 2.720 ms 8-bit @12 mhz 1.940 ms 8-bit @16 mhz 2.205 ms transmit command (rt-to-bc transfer) if the bus-65153 receives a valid transmit command word that the subsystem determines is legal (input illcmd is high) and the subsystem is not busy (input busy is high), the bus- 65153 will initiate a transmit data response following transmis- sion of the status word. this entails a handshake/read cycle for each data word, with the total number of data words to be transmitted specified by the word count field of the command word. a low on illcmd will result in the message error bit being set. no data words will be transmitted following transmission of the status word to an illegalized transmit command. a low on the busy input will set the busy bit in the status word; in this instance, only the status word will be transmitted, with no data words. receive command (bc-to-rt transfer) a dma handshake will be initiated for each word received over the 1553 data bus. if successful, the respective handshake will be followed by a corresponding write cycle. a handshake time- out will not terminate transfer attempts for the remaining data words, error flagging or status word transmission. after the reception of a valid nonmode code receive command word fol- lowed by the correct number of valid data words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the output good block received (gbr). rt-to-rt transfer errors if the t/r bit of the transmit command in an rt-to-rt transfer is a zero, the transmitting rt does not respond in time or an address mismatch is detected in the transmitting rt's status word, the bus-65153, as receiving rt, will classify the condition as a command error and will not respond. rt status, error handling, and message timing signals message transfer errors are indicated by means of the hs_fail, me, and rt_fail error indication outputs. additional error detection and indication mechanisms include updating of the internal status and bit word registers. the bus-65153 provides a number of timing signals during the processing of 1553 messages. nbgrt provides a negative pulse output following the receipt of a 1553 command word. incmd is asserted low when a new command is received. at the end of a message (either valid or invalid), incmd transitions from low to high. following the last data word of a valid nonmode code receive message, gbr is asserted low. me is asserted as a low output following any detected error in a received message. loopback test the bus-65153 performs a loopback self-test at the end of each nonbroadcast message processed. the loopback test consists of the following verifications: (1) the received version of every transmitted word is verified for validity (encoding, bit count, pari- ty) and correct sync type; (2) the first transmitted word (rt status word) is checked for correct rt address field; and (3) the received version of the last transmitted word is verified by means of a bit-by-bit comparison to the transmitted version of the word. if there is a transmitter timeout (668 ms) and/or the loopback test fails for one or more transmitted words, the terminal flag status word bit will be set in response to the next nonbroadcast message. status word the broadcast command received bit is formulated internally. the message error status bit will be set if the current command is a transmit status word or transmit last command mode command and if there was an error in the data portion of the pre- vious receive message. message error will also be set if illcmd has been sampled low for the current message. illcmd, service request, busy, and subsystem flag will be sampled from their respective status input pins approximately 5 ms fol- lowing the mid-parity bit zero crossing of the received command word. bit word the bus-65153 provides an internally formulated built-in-test word. this word is transmitted to the bc in response to a transmit bit word mode code command. internal built-in-test (bit) word definition d15: transmitter timeout d14: loop test failure - b bus d13: loop test failure - a bus d12: handshake failure d11: bus b transmitter shutdown d10: bus a transmitter shutdown d09: terminal flag inhibited d08: ch a / ch b d07: high word count d06: low word count d05: incorrect sync type received d04: invalid word received - manchester or parity error d03: rt-rt transfer response error (no gap, data sync, address mismatch) d02: rt-rt transfer no response timeout d01: rt-rt transfer - t/r error on second command or my valid address d00: command word contents error note: bits 15 through 9 are cleared only following a reset 7
input or reception of a reset remote terminal mode com- mand. bits 8 through 0 are updated as a result of every mes- sage processed. bit word bit descriptions transmitter timeout: set if the stic's failsafe timer detected a fault condition. the transmitter timeout circuit will automatically shut down the ch. a or ch. b transmitter if it trans- mits for longer than 668 m s . ch. b loop test failure, ch. a loop test failure: a loopback test is performed on the transmitted portion of every non-broadcast message. a validity check is performed on the received version of every word transmitted by the stic. in addi- tion, a bit-by-bit comparison is performed on the last word trans- mitted by the rt for each message. if either the received version of any transmitted word does not match the transmitted version and/or the received version of the last transmitted word is deter- mined to be invalid (sync, encoding, bit count, parity), or a fail- safe timeout occurs on the respective channel, the loop test failure bit for the respective bus channel will be set. handshake failure: if this bit is set, it indicates that the sub- system had failed to respond with the dma handshake input dtgrt asserted within the allotted time in response to the stic asserting dtreq. the allotted time for the subsystem's dtreq-to-dtgrt response time is approximately 3.0 to 3.7 ms for a dma write cycle and approximately 15.1 to 15.3 ms for a dma read cycle. ch. b transmitter shutdown, ch. a transmitter shutdown: indicates that the transmitter on the respective bus channel has been shut down by a transmitter shutdown mode code command received on the alternate channel. if an override transmitter shutdown mode code command is received on the alternate channel, this bit will revert back to logic 0. terminal flag inhibited: set to logic 1" if the stic's terminal flag rt status bit has been disabled by an inhibit terminal flag mode code command. will revert to logic 0 if an override inhibit terminal flag mode code command is received. ch. a/ch. b: logic 0 if the previous message was received on ch.a, logic 1 if the previous message was received on ch. b. high word count: set to logic 1 if the previous message had a high word count error. low word count: set to logic 1 if the previous message had a low word count error. incorrect sync type received: if set, indicates that the stic detected a command sync in a received data word. invalid word: indicates that the stic received one or more words containing one or more of the following error types: sync field error, manchester encoding error, parity error, and/or bit count error. rt-to-rt gap/sync/address error: this bit is set if the stic rt is the receiving rt for an rt-to-rt transfer and one or more of the following occur: (1) if the transmitting rt responds with a response time of less than 4 ms, per mil-std-1553b (mid-parity bit to mid-sync); i.e., less than 2 ms dead time; and/or (2) there is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting rt status word; and/or (3) the rt address field of the transmitting rt status word does not match the rt address in the transmit command word. rt-to-rt response timeout: if set, indicates that, for the previous message, the stic was the receiving rt for an rt-to- rt transfer and that the transmitting rt either did not respond or responded later than the stic's rt-to-rt timeout time. the stic's rt-to-rt response timeout time is defined as the time from the mid-bit crossing of the parity bit of the transmit command word to the mid-sync crossing of the transmitting rt status word. the value of the stic's rt-to-rt response timeout time is 18.9 m s . rt-to-rt second command error: if the stic is the receiving rt for an rt-to-rt transfer, this bit set indicates one or more of the following error conditions in the transmit command word: (1) t/r bit = logic 0; (2) subaddress = 00000 or 11111; (3) same rt address field as the receive command word. command word contents error: indicates a received command word is not defined in accordance with mil-std- 1553b. this includes the following undefined command words: (1) the command word is a non-mode code, broadcast, trans- mit command; (2) a message with a t/r bit of 0, a subad- dress/mode field of 00000 or 11111 and a mode code field between 00000 and 01111; (3) a mode code command that is not permitted to be broadcast (e.g., transmit status) is sent to the broadcast address 11111. 8
9 table 2. mil-std-1553b mode codes t/r bit mode code function data word broadcast allowed 1 00000 dynamic bus control no no 1 00001 synchronize no yes 1 00010 transmit status word no no 1 00011 initiate self test no yes 1 00100 transmitter shutdown no yes 1 00101 override transmitter shutdown no yes 1 00110 inhibit terminal flag no yes 1 00111 override inhibit terminal flag no yes 1 01000 reset remote terminal no yes 1 01001- 11111 reserved no tbd 1 10000 transmit vector word from subsystem no 0 10001 synchronize with data to subsystem yes 1 10010 transmit last command from internal register no 0 10100 selected transmitter shutdown (see note) to subsystem yes 0 10101 override selected transmitter shutdown (see note) to subsystem yes 1 10011 terrminal bit word from internal register no 0 10110- 11111 reserved yes tbd 1 10110- 11111 reserved yes tbd note: terminal responds with clear status but no action is taken, assuming a valid command word and any valid data word is received. broadcast mode code (subaddress 11111), t/r = 1 (note: use table 3e, but increase address by 2000) 3f80-3fff broadcast, transmit, subaddress 30 (undefined) 3f00-3f7f broadcast, transmit, subaddress 2 (undefined) 3100-317f broadcast, transmit, subaddress 1 (undefined) 3080-30ff broadcast mode code (subaddress 00000), t/r = 0 (note: use table 3d, but increase address by 2000) 3000-307f broadcast mode code (subaddress 11111), t/r = 0 (note: use table 3c, but increase address by 2000) 2f80-2fff broadcast, receive, subaddress 30 (see table 3a) 2f00-2f7f broadcast, receive, subaddress 2 (see table 3a) 2100-217f broadcast, receive, subaddress 1 (see table 3a) 2080-20ff broadcast mode code (subaddress 00000), t/r = 0 (note: use table 3b, but increase address by 2000) 2000-207f mode code (subaddress 11111), t/r = 1 (seetable 3e) 1f80-1fff transmit subaddress 30 (see table 3a) 1f00-1f7f receive, subaddress 2 (see table 3a) transmit, subaddress 2 (see table 3a) 1100-117f transmit, subaddress 1 (see table 3a) 1080-10ff mode code (subaddress 00000), t/r = 1 (seetable 3d) 1000-107f mode code (subaddress 11111), t/r = 1 (seetable 3c) 0f80-0fff receive, subaddress 30 (see table 3a) 0f00-0f7f receive, subaddress 1 (see table 3a) 0080-00ff mode code (subaddress 0000, t/r = 0), see (table 3b) 0000-007f function address (hex) 0100-017f table 3. overall memory map note: tables 3 and 3a-3d are byte-oriented addressing. mode codes all 13 of the dual redundant mil-std-1553b mode codes are implemented by the bus-65153. two mode codes, transmit vector word and synchronize (with data) involve data transfer with the subsystem. for the transmit bit word mode code, the internally formulated bit word is transmitted. table 2 provides a summary of the 1553b mode codes supported by the bus- 65153.
10 data word for mode code 11111, t/r = 0 (reserved) 0ffe, 0fff data word for mode code 10001, t/r = 0 (sync with data) 0fe2, 0fe3 not used (mode codes without data) 0fc0, 0fdf data word for mode code 10000, t/r = 0 (reserved) 0fe0, 0fe1 command word, t/r = 0, mode code 11111 (reserved) 0fbe, 0fbf command word, t/r = 0, mode code 10000 (reserved) 0fa0, 0fa1 command word, t/r = 0, mode code 10001 (sync with data) 0fa2, 0fa3 command word, t/r = 0, mode code 01111 (undefined) command word, t/r = 0, mode code 00000 (undefined) 0f80, 0f81 function address (hex) 009e, 009f table 3c. mode code memory map for subaddress 11111 t/r = 0 table 3b. mode code memory map for subaddress 00000,t/r = 0 001e, 001f address (hex) function 0000, 0001 command word, t/r = 0, mode code 00000 (invalid) command word, t/r = 0, mode code 01111 (invalid) 0022, 0023 command word, t/r = 0, mode code 10001 (sync with data) 020e, 0021 command word, t/r = 0, mode code 10000 (reserved) 003e, 003f command word, t/r = 0, mode code 11111 (reserved) 0060, 0063 data word for mode code 10000, t/r = 0 (reserved) 0040, 005f not used (mode codes without data) 0062, 0063 data word for mode code 10001, t/r = 0 ( sync with data) 007e, 007f data word for mode code 11111, t/r = 0 (reserved) table 3a. typical memory map of each non-mode code subaddress, 64 word block 0040, 0041 offset (hex) function 0000, 0001 command word 0002, 003f not used 0042, 0043 data word 1 data word 0 007e, 007f data word 31
11 data word for mode code 11111, t/r = 1 (reserved) 107e, 107f data word for mode code 10001, t/r = 1 (reserved) 1062, 1063 not used (mode codes without data) 1040, 105f data word for mode code 10000, t/r = 1 (transmit vector word) 1060, 1061 command word, t/r = 1, mode code 11111 (r eserved) 103e, 103f command word, t/r = 1, mode code 10000 (transmit vector word) 1020, 1021 command word, t/r = 1, mode code 10001 reserved) 1022, 1023 command word, t/r = 1, mode code 01111 ( reserved) command word, t/r = 1, mode code 00000 (dynamic bus control) 1000, 1001 function address (hex) 101e, 101f table 3d. mode code memory map for subaddress 00000, t/r = 1 data word for mode code 11111, t/r = 1 (reserved) data word for mode code 10001, t/r = 1 (reserved) 1fe2, 1fe3 not used (mode codes without data) 1fc0, 1fdf data word for mode code 10000, t/r = 1 (transmit vector word) 1fe0, 1fe1 command word, t/r = 1, mode code 11111 (reserved) 1fbe, 1fbf command word, t/r = 1, mode code 10000 (transmit vector word) 1fa0, 1fa1 command word, t/r = 1, mode code 10001(reserved) 1fa2, 1fa3 command word, t/r = 1, mode code 01111 (reserved) command word, t/r = 1, mode code 00000 (dynamic bus control) 1f80, 0f81 function address (hex) 1f9e, 1f9f table 3e. mode code memory map for subaddress 11111, t/r = 1
12 min max 0.97 1.56 0.87 symbol t12(@16mhz) description typ units t1(@12mhz) rt response time command mid-parity crossing to falling edge of nbgrt ms t1(@16mhz) command mid-parity crossing to falling edge of nbgrt ms t2(@12mhz) ms nbgrt pulse width ns t2(@16mhz) nbgrt pulse width ns t3 nbgrt rising edge to a6 falling edge ns t4(@12mhz) nbgrt falling edge to address valid ns t4(@16mhz) nbgrt falling edge to valid address ns t5(@12mhz) nbgrt falling edge to incmd falling edge ns t5(@16mhz) nbgrt falling edge to incmd falling edge ns t6(@12mhz) nbgrt falling edge to start of command word transfer cycle (note 2) ms t6(@16mhz) nbgrt falling edge to start of command word transfer cycle (note 2) ms t7 6.0 nbgrt falling edge to valid status inputs ms t8 6.76 incmd falling edge to cwc valid ns t9 data transfer cycle time (notes 2,3,4) ms t10 status inputs hold time ns t11(@12mhz) nbgrt rising to a6 rising (note 5) 3 ms t11(@16mhz) nbgrt rising to a6 rising (note 5) 3 ms t12(@12mhz) rt response time ms 1.38 140 190 100 150 45 300 410 220 330 800 865 590 655 1.19 1.28 0.88 0.97 4.1 5 60 500 6.18 6.96 figure 4. rt to bc (transmit) timing mid-parity t1 t2 t12 transmit command 1553 bus nbgrt ______ a6 (command/data) _______ a12(t/r),a11-a7(sa4-sa0) _ me, hs_fail ___ _______ ___ lmc, a13(brdcst/own addrs), _________ previous command present t4 t3 t11 c t5 t6 t8 t9 wc previous command a5-a1 (wc/mc4-0, cwc4-0) incmd _____ _____ dtreq, dtgrt, dtack, _____ _____ ____ wrt (note 1) illegal, servreq, _______ _______ ___ gbr __ data15-0, cs (note 1) ssflag, busy ______ ____ t7 t10 ______ rtfail see note 4
13 figure 4. rt to bc (transmit) timing (continued) 1.350 0.910 1.470 1.010 1.260 0.880 1.365 0.965 1.405 60 0.920 100 1.795 1.430 2.085 m s mid-partiy crossing of last data word to incmd rising t18(@16mhz) m s mid-partiy crossing of last data word to incmd rising 18(@12mhz) m s mid-sync crossing of last data word to wrt falling t17(@16mhz) m s mid-sync crossing of last data word to wrt falling t17(@12mhz) ms ns mid-sync crossing of status response to wrt rising end of data transfer cyle to valid next wc (note 3) t14(@12mhz) t16 ns m s t13 t15(@16mhz) m s t15(@12mhz) m s mid-sync crossing of status response to wrt rising t14(@16mhz) units typ description 1.700 1.305 0.840 max min mid-sync crossing of transmitted data to start of data transfer cycle (note 2) mid-sync crossing of status response to rtfail rising notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time references t6 and t15 are defined as the falling edge of dt_req. 3)the trailing edge of reference t9 and the leading edge of time reference t16 are defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. 5)if the command word transfer cycle is not complete (i.e., dt_req is still logic low) by the time indicated by the trailing ed ge of t11, a6 will be held low until the after transfer cycle is complete (60 ns max after the rising edge of dt_req). mid-sync crossing of transmitted data to start of data transfer cycle (note 2) mid-parity data mid-sync data mid-sync status mid-sync command t18 t9 t17 cwc=2 t16 cwc=1 t9 t15 t16 cwc=0 t14 t15 t13 symbol
14 min max 0.97 1.56 0.87 symbol description typ units t1(@12mhz) command mid-parity crossing to falling edge of nbgrt m s t1(@16mhz) command mid-parity crossing to falling edge of nbgrt m s t2(@12mhz) nbgrt pulse width ns t2(@16mhz) nbgrt pulse width ns t3 nbgrt rising edge to a6 falling edge ns t4(@12mhz) nbgrt falling edge to address valid, lmc ns t4(@16mhz) nbgrt falling edge to valid address, lmc ns t5(@12mhz) nbgrt falling edge to incmd falling edge ns t5(@16mhz) nbgrt falling edge to incmd falling edge ns t6(@12mhz) nbgrt falling edge to start of data transfer cycle m s t6(@16mhz) nbgrt falling edge to start of data transfer cycle (note 2) m s t7 nbgrt falling edge to valid status inputs m s t8 incmd falling edge to cwc valid ns t9 data transfer cycle time (notes 2,3,4) m s t10 status inputs hold time ns t11(@12mhz) first data word mid-parity crossing to a6 rising edge ns t11(@16mhz) first data word mid-parity crossing to a6 rising edge ns 1.38 140 190 100 150 45 300 410 220 330 800 865 590 655 1.19 1.28 0.88 0.97 4.1 5 60 500 820 1205 720 1025 figure 5. bc to rt (receive) timing see note 4 data mid-parity t1 t2 receive command previous command present command t3 t4 t5 t6 t8 t9 wc previous command t7 t10 1553 bus nbgrt _____ a6 (command/data) _______ a12(t/r),a11-a7(sa4-sa0) _ me, hs_fail __ _______ lmc, a13(brdcst/own addrs), ___ _________ a5-a1 (wc/mc4-0, cwc4-0) incmd _____ _____ dtreq, dtgrt, dtack, _____ _____ ___ wrt (note 1) illegal, servreq, _______ _______ ___ gbr __ data15-0, cs (note 1) ssflag, busy ______ ____ ______ rtfail
15 notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time references t6 and t13 are defined as the falling edge of dt_req. 3)the trailing edge of reference t9 and the leading edge of time reference t12 are defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. mid-parity status mid-sync data mid-parity t14 mid-parity present command t11 t16 t9 cwc=2 t12 t13 cwc=1 t12 t13 t9 cwc=0 t15 t17 t18 figure 5. bc to rt (receive) timing 150 100 190 140 3.29 3.17 3.37 3.23 3.46 3.26 3.57 3.36 100 6.76 6.0 1.94 6.96 ns gbr pulse width t18(@16mhz gbr pulse width t18(@12mhz) m s mid-parity crossing of status response to gbr falling t17(@16mhz) m s mid-parity crossing of status response to gbr falling t16(@12mhz) m s mid-parity crossing of status response to incmd rising t16(@16mhz) m s mid-parity crossing of status response to incmd rising t16(@12mhz m s mid-sync crossing of status response to rtfail rising t15 m s rt response time t14(@16mhz) ms m s mid-parity crossing of received data word to start of data transfer cycle (note 2) rt response time t13(@12mhz) t14(@12mhz) ns t12 units typ description symbol 1.52 6.18 60 max min end of data transfer cyle to valid next wc (note 3)
16 min max 0.97 1.56 0.87 symbol t12(@16mhz) description typ units t1(@12mhz) rt response time command mid-parity crossing to falling edge of nbgrt m s t1(@16mhz) command mid-parity crossing to falling edge of nbgrt m s t2(@12mhz) m s nbgrt pulse width ns t2(@16mhz) nbgrt pulse width ns t3 nbgrt rising edge to a6 falling edge ns t4(@12mhz) nbgrt falling edge to address valid ns t4(@16mhz) nbgrt falling edge to valid address ns t5(@12mhz) nbgrt falling edge to incmd falling edge ns t5(@16mhz) nbgrt falling edge to incmd falling edge ns t6(@12mhz) nbgrt falling edge to start of command word transfer cycle (note 2) m s t6(@16mhz) nbgrt falling edge to start of command word transfer cycle (note 2) m s t7 6.0 nbgrt falling edge to valid status inputs m s t8 6.76 incmd falling edge to cwc valid ns t9 data transfer cycle time (notes 2,3,4) m s t10 status inputs hold time ns t11(@12mhz) nbgrt rising to a6 rising (note 5) 3 m s t11(@16mhz) nbgrt rising to a6 rising (note 5) 3 m s t12(@12mhz) rt response time m s 1.38 140 190 100 150 45 300 410 220 330 800 865 590 655 1.19 1.28 0.88 0.97 4.1 5 60 500 6.18 6.96 figure 6. rt to rt (transmit) timing see note 4 mid-parity t1 t2 t12 transmit command receive command previous command previous command present command t4 t5 t8 wc t3 t11 cwc=0 t6 t7 t9 t10 1553 bus nbgrt _____ a6 (command/data) _______ lmc, a13(brdcst/own addrs), a12(t/r),a11-a7(sa4-sa0) ___ _________ _ a5-a1 (wc/mc4-0, cwc4-0) incmd _____ __ _______ me, hs_fail illegal, servreq, ssflag, busy ______ ____ _______ _______ ___ gbr dtreq, dtgrt, dtack, _____ _____ _____ data15-0, cs (note 1) ___ ___ wrt (note 1) rtfail ______
17 notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time references t6 and t15 are defined as the falling edge of dt_req. 3)the trailing edge of reference t9 and the leading edge of time reference t16 are defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. 5)if the command word transfer cycle is not complete (i.e., dt_req is still logic low) by the time indicated by the trailing ed ge of t11, a6 will be held low until the after transfer cycle is complete (60 ns max after the rising edge of dt_req). mid-parity status data data mid-sync status mid-sync mid-sync t16 cwc=1 cwc=2 t16 t18 t9 t15 t17 t13 t14 t15 t9 figure 6. rt to rt (transmit) timing (continued) 1.350 0.910 1.470 1.010 1.260 0.880 1.365 0.965 60 1.795 1.430 1.405 2.085 m s mid-partiy crossing of last data word to incmd rising 18(@16mhz) m s mid-partiy crossing of last data word to incmd rising t18(@12mhz) m s mid-sync crossing of last data word to wrt falling t17(@16mhz) m s mid-sync crossing of last data word to wrt falling t17(@12mhz ns end of data transfer cyle to valid next wc (note 3) t16 m s mid-sync crossing of transmitted data to start of data transfer cycle (note 2) t15(@16mhz) m s m s mid-sync crossing of status response to wrt rising mid-sync crossing of transmitted data to start of data transfer cycle (note 2) t14(@12mhz) t15(@12mhz) ns m s mid-sync crossing of status response to rtfail rising mid-sync crossing of status response to wrt rising t13 t14(@16mhz) units typ description symbol 0.920 1.700 100 1.305 0.840 max min
18 figure 7. rt to rt (receive) timing 1025 720 1205 820 500 60 5 4.1 0.97 0.88 1.28 1.19 655 590 865 800 330 220 410 300 45 150 100 190 140 1.38 ns a6 pulse width t11(@16mhz) ns a6 pulse width t11(@12mhz) ns status inputs hold time t10 m s data transfer cycle time (notes 2,3,4) t9 ns incmd falling edge to cwc valid t8 m s nbgrt falling edge to valid status inputs t7 m s nbgrt falling edge to start of data transfer cycle (note 2) t6(@16mhz) m s nbgrt falling edge to start of data transfer cycle t6(@12mhz) ns nbgrt falling edge to incmd falling edge t5(@16mhz) ns nbgrt falling edge to incmd falling edge t5(@12mhz) ns nbgrt falling edge to valid address, lmc t4(@16mhz) ns nbgrt falling edge to address valid, lmc t4(@12mhz) ns nbgrt rising edge to a6 falling edge t3 ns t2(@16mhz) ns nbgrt pulse width t2(@12mhz) m s command mid-parity crossing to falling edge of nbgrt t1(@16mhz) m s command mid-parity crossing to falling edge of nbgrt t1(@12mhz) units typ description symbol 0.87 1.56 0.97 max min see note 4 t2 t3 t11 transmit command receive command mid-parity t1 1553 bus me, hs_fail __ _______ nbgrt _____ _______ a6 (command/data) a12(t/r),a11-a7(sa4-sa0) lmc, a13(brdcst/own addrs), ___ _________ _ a5-a1 (wc/mc4-0, cwc4-0) incmd _____ ___ wrt (note 1) previous command previous command present command t4 t5 t8 cwc=0 wc t6 t7 t9 t10 illegal, servreq, ssflag, busy ______ ____ _______ _______ ___ gbr rtfail ______ dtreq, dtgrt, dtack, _____ _____ _____ __ data15-0, cs (note 1) rt to rt (receive) timing digram nbgrt pulse width
19 status mid-sync mid-parity data mid-parity t14 data mid-parity status cwc=1 t12 t12 t16 cwc=2 t17 t18 t15 t13 t9 t9 t13 notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time references t6 and t13 are defined as the falling edge of dt_req. 3)the trailing edge of reference t9 and the leading edge of time reference t12 are defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. min max 1.23 60 1.57 1.52 6.18 symbol description typ units t12 t13(@16mhz) end of data transfer cyle to valid next wc (note 3) mid-parity crossing of received data word to start of data transfer cycle (note 2) ns m s t13(@12mhz) t14(@12mhz) mid-parity crossing of received data word to start of data transfer cycle (note 2) rt response time m s m s t14(@16mhz) rt response time m s t15 mid-sync crossing of status response to rtfail rising ns t16(@12mhz) mid-parity crossing of status response to incmd rising m s t16(@16mhz) mid-parity crossing of status response to incmd rising m s t17(@12mhz) mid-parity crossing of status response to gbr falling m s t17(@16mhz) mid-parity crossing of status response to gbr falling m s 18(@12mhz) gbr pulse width ns t18(@16mhz) gbr pulse width ns 1.94 6.96 6.0 6.76 100 3.36 3.57 3.26 3.45 3.23 3.37 3.17 3.29 140 190 100 150 figure 7. rt to rt (receive) timing (continued)
20 mid-parity t1 t 2 receive command 1553 bus nbgrt _____ a6 (command/data) _______ _______ hs_fail me __ previous command previous command lmc, a13(brdcst/own addrs), ___ _________ a12(t/r),a11-a7(sa4-sa0) _ a5-a1 (wc/mc4-0, cwc4-0) incmd _____ ___ wrt (note 1) dtreq, dtgrt, dtack, _____ _____ __ data15-0, cs (note 1) _____ illegal, servreq, ssflag, busy ______ _______ _______ ____ ___ gbr rtfail ______ min max 0.97 1.56 0.87 symbol description typ units t1(@12mhz) command mid-parity crossing to falling edge of nbgrt m s t1(@16mhz) command mid-parity crossing to falling edge of nbgrt m s t2(@12mhz) nbgrt pulse width ns t2(@16mhz) nbgrt pulse width ns t3 nbgrt rising edge to a6 falling edge ns t4(@12mhz) nbgrt falling edge to address valid, lmc ns t4(@16mhz) nbgrt falling edge to valid address, lmc ns t5(@12mhz) nbgrt falling edge to incmd falling edge ns t5(@16mhz) nbgrt falling edge to incmd falling edge ns t6(@12mhz) nbgrt falling edge to start of data transfer cycle m s t6(@16mhz) nbgrt falling edge to start of data transfer cycle (note 2) m s t7 nbgrt falling edge to valid status inputs m s t8 incmd falling edge to cwc valid ns t9 data transfer cycle time (notes 2,3,4) 1.38 140 190 100 150 45 300 410 220 330 800 865 590 655 1.19 1.28 0.88 0.97 4.1 5 60 figure 8. bc to rt (receive) message error timing see note 4
21 data mid-parity t11 2 data (parity error) present command t3 t4 t12 t13 t14 wc t5 t8 cwc=0 wc t6 t7 t9 t10 min 5.95 500 5.87 max 6.26 6.245 45 t11(@12mhz) t10 t11(@16mhz) description mid-parity crossing of data word with even parity to falling edge of me status inputs hold time mid-parity crossing of data word with even parity to falling edge of me typ figure 8. bc to rt (receive) message error timing units ms ns m s t12 me falling edge to a6 high ns 300 360 t13(@12mhz) me falling edge to incmd rising edge ns 220 280 t13(@16mhz) me falling edge to incmd rising edge ns 75 t14 incmd rising edge to word count valid notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time reference t6 is defined as the falling edge of dt_req. 3)the trailing edge of reference t9 is defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. ns symbol
22 t2 transmit command receive command mid-parity t1 previous command previous command present command t3 t4 t5 t8 t11 cwc=0 wc t6 t7 t9 t10 1553 bus _______ nbgrt _____ me __ a6 (command/data) _______ lmc, a13(brdcst/own addrs), a12(t/r),a11-a7(sa4-sa0) ___ _________ _ a5-a1 (wc/mc4-0, cwc4-0) incmd _____ hs_fail ___ dtreq, dtgrt, dtack, _____ _____ _____ __ illegal, servreq, ssflag, busy ______ ____ _______ _______ gbr ______ data15-0, cs (note 1) ___ wrt (note 1) rtfail min max 0.97 1.56 0.87 symbol description typ units t1(@12mhz) command mid-parity crossing to falling edge of nbgrt ms t1(@16mhz) command mid-parity crossing to falling edge of nbgrt ms t2(@12mhz) nbgrt pulse width ns t2(@16mhz) nbgrt pulse width ns t3 nbgrt rising edge to a6 falling edge ns t4(@12mhz) nbgrt falling edge to address valid, lmc ns t4(@16mhz) nbgrt falling edge to valid address, lmc ns t5(@12mhz) nbgrt falling edge to incmd falling edge ns t5(@16mhz) nbgrt falling edge to incmd falling edge ns t6(@12mhz) nbgrt falling edge to start of data transfer cycle ms t6(@16mhz) nbgrt falling edge to start of data transfer cycle (note 2) ms t7 nbgrt falling edge to valid status inputs ms t8 incmd falling edge to cwc valid t9 data transfer cycle time (notes 2,3,4) 1.38 140 190 100 150 45 300 410 220 330 800 865 590 655 1.19 1.28 0.88 0.97 4.1 5 60 figure 9. rt to rt (receive) timeout timing see note 4
23 figure 9. rt to rt (receive) timeout timing (continued) ns ns a6 pulse width incmd rising edge to word count valid t11(@12mhz) t14 1205 75 820 ns ns status inputs hold time me falling edge to incmd rising edge t10 t13(@16mhz) 280 500 220 ns me falling edge to incmd rising edge t13(@12mhz) 360 300 ns ms a6 pulse width rt-rt no response timeout (message error) t11(@16mhz) t12 units typ description symbol 1025 19.5 720 18.25 max min notes: 1)if addr_ena is logic 1, cs, wrt, and a13..a0 will be in a high impedance state except for when a word transfer is being per formed (dt_ack = logic 0). 2)the leading edge of time reference t9 and the trailing edge of time reference t6 is defined as the falling edge of dt_req. 3)the trailing edge of reference t9 is defined as the rising edge of dt_req. 4)data transfer cycle timing information is described in other figures. data status t12 wc t13 t14
24 t1 t12 t2 t4 t6 t8 t5 t7 t10 t9 valid valid t3 dt_req dt_grt dt_ack wr (see note 1) cs (see note 1) a05-a01 db15-db00 (output) addr. window (see note 1) t11 max 3.0 symbol t12 typ t1(@12mhz) dt_ack high delay to address, wrt, cs tri-state (note 1) dma request to dma grant (command word) m s t1(@16mhz) dma request to dma grant (command word) m s t1(@12mhz) ns dma request to dma grant (data word) m s t1(@16mhz) dma request to dma grant (data word) m s t2 dma grant pulse width ns t3 dma grant delay to dma acknowledge ns t4 dt_ack pulse width ns t5 dt_ack low delay to address enabled (note 1) ns t6(@12mhz) dt_ack low delay to rising edge of cs ns t6(@16mhz) dt_ack low delay to rising edge of cs ns t7(@12mhz) data valid setup time to rising edge of cs ns t7(@16mhz) data valid setup time to rising edge of cs ns t8(@12mhz) 45 cs low pulse width ns t8(@16mhz) cs low pulse width ns t9(@12mhz) data hold time following rising edge of cs ns t9(@16mhz) data hold time following rising edge of cs ns t10 data tri-state setup time prior to rising edge of dt_req, dt_ack ns t11 dt_req high delay to address update (note 1) ns 3.3 3.5 3.7 130 130 485 515 35 315 365 360 410 195 255 150 185 170 205 70 50 10 60 figure 10. dma write 16-bit note: 1)diagram assumes addr_ena is set to logic 0. if is was set to logic 1, then a13-a00, cs, and wrt would normally be high im pedance until activated by dt_ack as shown by addr. window timing. description min units
25 t1 t11 t2 t4 t5 t8 t6 t9 valid t3 dt_req dt_grt dt_ack wr (see note 1) cs (see note 1) a05-a01 db15-db00 address window (see note 1) t10 valid t7 nin max 15.1 symbol 112 typ units t1(@12mhz) dt_ack high delay to address, wrt, cs tri-state (note 1) dma request to dma grant m s t1(@16mhz) dma request to dma gran) m s ns t5(@12mhz) t2 dt_ack low delay to cs low dma grant pulse width ns t3 dma grant delay to dma acknowledge ns t4 ns dt_ack pulse width ns t5(@16mhz) 70 dt_ack low delay to cs low ns 115 t6 dt_ack low delay to address, wrt, cs, enabled (note 1 ns t7(@12mhz) data valid setup time to rising edge of cs ns t7(@16mhz) data valid setup time to rising edge of cs ns t8(@12mhz) 45 cs low pulse width ns t8(@16mhz) cs low pulse width ns t9(@12mhz) data hold time following cs high ns t10 dt_req high delay to address update (note 1) ns 15.3 130 130 485 515 50 95 35 180 240 315 345 360 390 0 60 figure 11. dma read 16-bit note: 1)diagram assumes addr_ena is set to logic 0" if is was set to logic 1, then a13-a00, cs, and wrt would normally be high im pedance until activated by dt_ack as shown by address window timing. description
26 min max 3.0 symbol t11(@12mhz) description typ units t1(@12mhz) data hold time following rising edge of cs dma request to dma grant (command word) m s t1(@16mhz) dma request to dma grant (command word) m s t1(@12mhz) ns dma request to dma grant (data word) m s t1(@16mhz) t14 dma request to dma grant (data word) m s t2 dt_ack high delay to address, wrt, cs high impedance (note 1) dma grant pulse width ns t3 dma grant delay to dma acknowledge ns t4 ns dt_ack pulse width ns t5 dt_ack low delay to a0 low (upper byte transfer cycle time ns t6(@12mhz) 45 start of byte transfer cycleto rising edge of cs ns t6(@16mhz) t11(@16mhz) start of byte transfer cycleto rising edge of cs ns t7 data hold time following rising edge of cs data tri-state hold time following start of byte transfer ???ns 70 t8 dt_ack low delay to address, wrt, cs enabled (note 1) ???ns t9(@12mhz) ns data setup time prior to rising edge of cs ns t9(@16mhz) t12 data setup time prior to rising edge of cs ns t10(@12mhz) data tri-state setup time prior to end of byte transfer cycle cs pulse width ns t10(@16mhz) cs pulse width ns 3.3 3.5 3.7 130 130 985 1015 485 515 315 365 360 410 50 35 195 255 150 170 ns figure 12. dma write 8-bit 50 10 t13 dt_req high delay to address update (note 1) ns 60 t1 t2 t4 t5 t8 t10 t14 t11 valid t3 dt_req dt_grt dt_ack wr (see note 1) cs (see note 1) a05-a01 db15-db00 (output) addr. window (see note 1) t13 t6 t10 t6 a00 valid valid t9 t11 t9 t17 t12 upper byte (15..8) t12 lower byte (7..0) t17 note: 1)diagram assumes addr_ena is set to logic 0. if is was set to logic 1, then a13-a00, cs, and wrt would normally be high im pedance until activated by dt_ack as shown by addr. window timing.
27 t1 t2 t4 t5 t7 valid t3 dt_req dt_grt dt_ack wr (see note 1) cs (see note 1) a05-a01 db15-db00 (output) addr. window (see note 1) t11 t8 a00 upper byte (15..8) lower byte (7..0) valid valid t6 t9 t10 t3 t6 t9 t10 min max 15.1 symbol 112 description typ units t1(@12mhz) dt_ack high delay to address, wrt, cs tri-state (note 1) dma request to dma grant m s t1(@16mhz) dma request to dma gran) m s t6(@16mhz) ns start of byte transfer cycle to falling edge of cs ns 50 t5 95 t2 dt_ack delay to a0 low (upper byte transfer cycle time) dma grant pulse width ns t3 dma grant delay to dma acknowledge ns t4 ns ns 485 515 t6(@12mhz) start of byte transfer cycle to falling edge of cs ns t7 dt_ack low delay to address, wrt, cs enabled (note 1) ns t8(@12mhz) 45 cs pulse width ns t8(@16mhz) cs pulse width ns t10 data hold time following cs high ns t11 dt_req high delay to address update (note 1) ns 15.3 130 130 985 1015 70 115 35 315 345 360 390 0 60 note: 1)diagram assumes addr_ena is set to logic 0. if is was set to logic 1, then a13-a00, cs, and wrt would normally be high im pedance until activated by dt_ack as shown by addr. window timing figure 13. dma read 8-bit dt_ack pulse widthack pulse width
28 max 3.2 3.3 3.5 symbol description transfer typ figure 14. dma handshake failure units t1(@12mhz) dt_req pulse width command word write m s t1(@16mhz) dt_req pulse width command word write m s t6(@16mhz) dt_req rising edge to wrt low data word read ns 220 310 3.7 3.8 t2 dt_grt high hold time from dt_req rising all ns t3 hs_fail falling edge from dt_req rising edge all ns t4 word count valid from dt_req rising edge all ns 3.9 t1(@12mhz) dt_req pulse width data word write t6(@12mhz) m s dt_req rising edge to wrt low data word read ns t1(@16mhz) dt_req pulse width data word write m s 4.0 15.3 t1(@12mhz) dt_req pulse width data word write m s t1(@16mhz) dt_req pulse width data word write 3.6 m s 15.5 -60 25 60 300 400 min notes: 1)diagram assumes addr_ena is set to logic 0. if it was set to logic 1 then a13-a00, cs and wrt would normally be in high i mpedance until activated by dt_ack as shown by addr. window timing. 2)if the transfer requested was a read operation, and a handshake failure occurred, then the wrt signal would return to the wri te state and the bus-65153's transmission of the 1553 bus would terminate at the conclusion of the preset word. t1 _ _ _ _ _ _ dt_req dt_grt _ _ _ _ _ _ t2 t3 t4 a05 - a01 hs_fail _ _ _ _ _ _ _ (note 1) _ _ _ wrt (notes 1,2) t5
29 z o (70 to 85 w ) z o (70 to 85 w ) 55 ohm 55 ohm 1 2 3 4 8 31 vpp 1.4:1 direct coupled (short stub) 44 vpp bus-65153 bus-65163 or 44 vpp transformer 1 2 3 5 7 isolation 2:1 22 vpp transformer coupled (long stub) 1 3 4 8 1:1.4 31vpp 0.75z o 0.75z o transformer coupling transformer isolation direct coupled (short stub) 33 vpp bus-65154 bus-65164 transformer 1 2 3 4 8 isolation 28 vpp 1:0.83(or 1:0.80) 55 ohm 55 ohm 0.75z o 0.75z o 1 3 4 8 1:1.4 28 vpp 1 2 3 5 7 20 vpp transformer coupled (long stub) 1:0.6 or 33 vpp transformer isolation transformer coupling 1 ft max 1 ft max 20 ft max 20 ft max interface to mil-std-1553 bus interfacing the bus-65153 to a mil-std-1553 bus requires a pair of pulse transformers. these transformers, or qpl equiva- lents, are available from beta transformer technology corporation, a subsidiary of ddc. the bus-65153 hybrid and beta transformers may be wired for either direct coupled or stub coupled configurations. the recommended transformer for each of the bus-65153 transceiver options is listed in table 4. the interface between a bus-65153 and a mil-std-1553 bus is illustrated in figure 15.notes for table 4: notes for table 4: (1)shown for one of two redundant buses that interface to the bus- 65153 hybrid. (2)transmitted voltage level on 1553 bus is 6 vp-p min, 7 vp-p nomi- nal, 9 vp-p max. (3)required tolerance on isolation resistors is 2%. instantaneous power dissipation (when transmitting) is approximately 0.5 w (typ), 0.8 w (max). (4)transformer pin numbering is correct for ddc bus-25679 or bus- 29854 transformer. for the beta transformer (e.g., b-2203) or the qpl- 21038-31 transformer (e.g., m21038/27-02), the winding sense and turns ratio are mechanically the same, but the pin numbering is reversed. therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 in the diagram for the beta or qpl transformers. (5) the b-2204, b-2388, and b-2344 transformers have a slightly differ- ent turns ratio on the direct coupled taps then the turns ratio of the bus-29854 direct coupled taps. they do, however, have the same transformer coupled ratio. for transformer coupled applications, either transformer may be used. the transceiver in the bu-65170x2 and the bu-61580x2 was designed to work with a 1:0.83 ratio for direct cou- pled applications. for direct coupled applications, the 1.20:1 turns ratio is recommended, but the 1.25:1 may be used. the 1.25:1 turns ratio will result in a slightly lower transmitter amplitude. (approximately 3.6% lower) and a slight shift in the ace's receiver threshold. figure 15. bus-65153 and bus-65154 to mil-std-1553 interface table 4. recommended beta transformeer device transformer bus-65153/63 bus-25679, b-2203, lpb-5002 lpb-5009, or m21038/27-02 bus-65154/64 bus-29854, b-2204 lpb-5001, lpb-5008 or m21038/27-03
simple system interface figure 16 illustrates the capability of the stic to operate in a system with no host processor. a simple linear addressing scheme is used that can be easily decoded to form read and write signals for direct access to data buffers or data latches. a double buffered mechanism may be used on received data in order to maintain data validity and consistency. the latched discrete outputs section of the drawing uses two sets of latches. the first latch is updated when the received data word is transferred from the stic. the second latch is not updat- ed until the message is validated, as indicated by the signal good block received (gbr). if an error, such as parity or manchester, occurs on a received data word, all the data asso- ciated with that message will be ignored, thus fulfilling the data validity/consistancy requirement. dma interface the stic may be interfaced to a host processor by means of a simple dma interface. the address and control lines may be placed in a three-state mode by setting the addr_ena signal to logic 1. while the stic is not accessing the ram (i.e., dt_ack is logic 1) the address, data, and control lines (cs, wrt) are held in a high impedance state. the signals cs and wrt require pull-up resistors. the stic may be programmed to operate in either a 16-bit transfer mode (figure 17) or an 8-bit transfer mode (figure 18). in 16-bit mode (db_sel set to logic 0) the signal a0 is not used (always logic 1) and 16-bit transfers are performed on data lines d0..d15. in 8-bit mode (db_sel set to logic 1) the signal a0 is used to indicate whether the upper (msb) data byte (a0 set to logic 1) or the lower (lsb) data byte (a0 set to logic 0) is being transferred. the upper and lower data bytes are not multiplexed internally, therefore, the signals must be connected externally. d0 must be connected to d8, d1 must be connected to d9, ... , and d7 must be connected to d15 30 figure 16. bus-65153 minimum complexity system q latch latch dq d w0 write address decoder cs a0..a13 _ _ wn vcc d q _ q latched discrete outputs q latch latch dq d bus 65153 "stic" vcc d _ q tri-state buffer q nbgrt gbr _ _ _ _ _ _ _ _ address decoder read r0 discrete buffered inputs tri-state buffer rn db grt db0..db15 _ _ _ _ _ _
31 figure 18. bus-65153 8-bit dma interface figure 17. bus-65153 16-bit dma interface bus grant _ _ _ _ _ _ _ _ _ _ _ bus request bus acknowledge _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ dt req dt gnt _ _ _ _ _ _ _ _ _ _ _ _ dt ack _ _ _ _ _ _ rx/tx a rx/tx a _ _ _ _ _ _ _ rx/tx b rx/tx b _ _ _ _ _ _ _ vcc bus-65153 db0..db15 me _ _ _ _ _ _ _ rt_add_err _ _ _ _ _ _ _ _ _ _ a01..a13 _ _ a00 a01 a02 a03 a04 a05 a0 a1 a2 a3 a4 d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 d0..d15 a1..a13 host processor a06 a07 a08 a09 a10 a11 a12 a13 a5 a6 a7 a8 a9 a10 a11 a12 d5 d6 d7 d8 d9 d10 d11 d12 d13 d5 d6 d7 d8 d9 d10 d11 d12 d13 hs fail _ _ _ _ _ _ _ incmd _ _ _ _ _ gbr _ _ _ rt fail nbgrt _ _ _ _ _ "stic" rt ad 4 rt ad 3 rt ad 2 rt ad 1 rt ad 0 rt ad p tx inh _ _ _ _ _ _ addr_ena _ _ _ _ _ _ _ _ db_sel _ _ _ _ _ _ _ rt ad latch vcc cs _ _ _ _ _ vcc cs we oe d14 d15 d14 d15 8kx16 ram data strobe _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ read/write wrt clock in clock sel 12 mhz osc vcc illegal _ _ _ _ _ _ _ reset _ _ _ _ _ servreq ssflag _ _ _ _ _ _ busy _ _ _ _ vcc bus request bus grant _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ dt req dt gnt _ _ _ _ _ _ _ _ _ _ _ _ rx/tx a rx/tx a rx/tx b rx/tx b _ _ _ _ _ _ _ _ _ _ _ _ _ _ db0..db07 a00..a13 dt ack _ _ _ _ _ _ db8..db15 _ _ bus acknowledge _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ a0 a00 a00..a13 d0..d7 d0 d0 host processor d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d7 a01 a02 a03 a04 a05 a06 a07 a08 a09 a1 a2 a3 a4 a5 a6 a7 a8 a9 me hs fail _ _ _ _ _ _ _ _ _ _ _ _ _ _ incmd _ _ _ _ _ rt_add_err _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ gbr _ _ _ rt fail "stic" rt ad 4 rt ad 3 rt ad 2 rt ad 1 rt ad 0 bus-65153 rt ad latch vcc vcc rt ad p tx inh _ _ _ _ _ _ addr_ena _ _ _ _ _ _ _ _ nbgrt vcc a10 a11 a12 a13 cs we oe a10 a11 a12 a13 data strobe _ _ _ _ _ _ _ _ _ _ _ read/write _ _ _ _ _ 16kx8 ram cs wrt _ _ _ _ _ clock sel db_sel servreq _ _ _ _ _ _ _ ssflag _ _ _ _ _ _ busy _ _ _ _ 12 mhz clock in vcc osc illegal _ _ _ _ _ _ _ reset _ _ _ _ _
p.c. board layout guidelines ground planes as is the rule in all high speed digital circuits, it is good practice to use ground and power supply planes under the stic hybrid as well as the associated components. the reason for not using supply or ground planes under the ana- log signal traces is that the effect of the distributed capacitance will be to lower the input impedance of the terminal, as seen from the 1553 bus. mil-std-1553 requires a minimum input imped- ance of 2000 ohms for direct coupled terminals and 1000 ohms for transformer (stub) coupled terminals. if there are ground planes under the analog bus signal traces, it is likely that the ter- minal will not meet this requirement. power and ground distribution another important consideration is power and ground distribu- tion. refer to figure 19. for the stic hybrid/transformer com- bination, the high current path when the stic is transmitting will be from the -15 volt power supply, through the transmitter output stage, through one leg of the isolation transformer to the trans- former center tap. it is important to realize that the high current return path is through the transformer center tap and not through the stic's gnd pin. it is an important layout consideration to minimize the power supply distribution impedance along this path. any resistance will result in voltage drops for the power supply input voltage, and can ultimately lower the transmitter output voltage, possibly below the minimum level required by mil-std-1553. 1553 bus connections the isolation transformers should be placed as physically close as possible to the respective tx/rx pins on the stic and the distance from the isolation transformers to any connectors or cables leaving the board should be as short as possible. in addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and trans- former-to-connector spacings serves to minimize crosstalk from other signals on the board. the general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. this minimizes impedance discontinuities. the decision of whether to isolate or make connections between the center tap of the isolation trans- former's secondary, the stub shield, the bus shield, and/or chas- sis ground must be made on a system basis, as determined by an analysis of emi/rfi and lightning considerations. in most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. this is 32 figure 19. power/ground current distribution it is very important that there be no ground and/or power supply planes under- neath any of the analog bus signal traces- this applies to the tx/rx signals running from the stic hybrid to the transformers as well as from the transformers to any connectors or cables leaving the board logic rx transceiver tx 1 2 3 6 8 7 5 4 bus-41429 high level currents low level currents low level currents logic gnd gnd a/b +5 v logic +5 v a/b -15 v/-12 v (a/b) bus-29854 bus-25679
despite the fact that the mil-std-1553b requirement is for it to be measured looking directly in from the bus side of the isolation transformer. the effect of a relatively long stub cable will be to reduce the measured impedance. in order to keep the impedance above the required level of 1000 ohms (for transformer-coupled stubs), the length of any cable between the 1553 rt and the system con- nector should be minimized. simulated bus (lab bench) interconnections for purposes of software development and system integration, it is gen- erally not necessary to integrate the required couplers, terminators, etc., that comprise a complete mil-std-1553b bus. in most instances, a sim- plified electrical configuration will suffice. the three connection methods illustrated in figure 20 allow the stic to be interfaced over a ?simulat- ed busa to simulation and test equipment. it is important to note that the termination resistors indicated are necessary in order to ensure reli- able communications between the stic and the simulation/test equip- ment. 33 figure 20. simulated bus (lab bench) interconnections a) direct coupled to direct coupled (b) transformer coupled to transformer coupled (c) direct coupled to transformer coupled 1 2 3 8 7 5 4 stic hybrid test/ simulation equipment stub coupling stub coupling isolation transformer 78 w 1.5w (a) 1 2 3 8 4 stic hybrid test/ simulation equipment direct coupling direct coupling isolation transformer 39 w 0.5w (b) 55 w 1w 55 w 1w 55 w 55 w 1 2 3 8 4 stic hybrid test/ simulation equipment stub coupling direct coupling isolation transformer 39 w 0.5w (c) 55 w 1w 55 w 1w 20 w 0.5w 20 w 0.5w
34 power and ground table 5. bus-65153 pin descriptions pin no description i/o name 18 analog and digital ground - gnd 36 70 35 ch. a and ch. b transceiver -15v (-12v) supply input ch.b transceiver +5v supply input logic and ch. a transceiver +5v supply input i i i -15 (-12) volts +5 volts b +5 va i/o i/o i/o db00 (lsb) db02 db10 26 24 15 i/o i/o i/o db01 db03 db11 25 23 14 i/o i/o db04 db12 22 13 8/16-bit data bus. db15 through db00 may be configured as either a 16-bit or an 8-bit data bus. in the 8-bit mode, db15 thru db8 should be connected directly to db7 thru db0, respectively (db15 to db7, db14 to db6 , ... , db8 to db0). db15-db00 is maintained in a high-impedance state except when the bus-65153 is performing a data write transfer. in the 8-bit mode, the upper byte is transferred first, followed by the lower byte. i/o i/o db05 db13 21 12 description i/o i/o i/o i/o i/o i/o i/o db06 db14 20 11 db07 db15 (msb) 19 10 db08 name 17 pin no db09 16 (table 5 continues on the next page.) data bus (16)
35 a11 through a07 : subaddress [4:0] - these outputs are the latched data from the subaddress field of the received command word. they are updated after nbgrt but before incmd goes active. they are cleared by reset. a11 corresponds to sa4 which is the msb and a07 corresponds to sa0 which is the lsb. (note 1) o a07 (lsb) 57 o o a00 a08 64 56 o o a01 (lsb) a09 63 55 o o a02 a10 62 54 table 5. bus-65153 pin descriptions - continued address bus (14) description transmit/receive - latched output signal that represents the latched t/r bit (bit 10) of the present command word. it is updated after nbgrt but before incmd goes active. a logic 1 indicates a transmit command, a logic 0 indicates a receive command. cleared by reset. (note 1) o i/o o o o o o o a03 a11 (msb) 61 53 a04 a12 60 52 a05 (msb) a13 59 50 a06 name 58 a05 through a01 (lsb):word count [4:0] / current word count [4:0]. multiplexed output signals which are defined as follows: these outputs are the latched data from the word count field of the received command word. they are updated after nbgrt but before incmd goes active. they are cleared by reset. for the command word transfer (a06 = 0) of a nonmode code command word, a05-a00 will be 00000. for a mode code command word transfer, a05-a00 will reflect the mode code field of the command word. if the present command is not a mode code and incmd is active then these lines become the output of a current word counter. that is, when incmd goes active, these outputs go to logic 0 and are then incremented after every data word transfer or handshake timeout. for a mode code transfer, the single data word is accessed at an address location that is offset by a value of 32 above that of the location for the corresponding command word. when incmd goes inac- tive, a05-a01 become the latched word count field again. a5 corresponds to wc4 which is the msb and a1 cor- responds to wc0 which is the lsb. (note 1) transmitter inhibit. a low level on this input disables both 1553 transmitters. i txinh 49 description clock, reset, and transmitter inhibit (4) 12 or 16 mhz clock input. clock frequency select. if high, selects 12 mhz clock input. if low, selects a 16 mhz clock input. master reset - active low input signal (2 clock cycles minimum) used to reset the entire circuit. i/o i i i reset 45 clocksel 43 clock in 51 name notes: 1. a13 through a0, cs, and wrt will be placed in a high impedance state if addr_ena is high and dtack is inactive (high). 2. the rt status word inputs illcmd, servreq, ssflag, and busy are sampled approximately 5 ms following the mid-parity bit zero crossing of the received command word. pin no. (table 5 continues on the next page.) broadcast. latched output signal that represents the rt address field of the present command word. that is, it was either a broadcast message (all ones in the rt address field) or a command addressed explicitly to this ter- minal (the address field of the command word matches the terminals's rtadd04 to rtadd0 inputs and rtad4- 0, rtadp has an odd parity sum.). it is updated after nbgrt but before incmd goes active. a logic 1 indicates a broadcast command, a logic 0 indicates a command to the bus-65153's rt address. cleared by reset. (note 1) command word transfer - active low level output signal that is asserted when the 1553 command word is being transferred to the subsystem over the parallel data bus. a06 is high during all data word transfers. (note 1) msb/lsb - output signal that is used during 8-bit data transfers to indicate which byte of the present 16-bit word is being transferred. a logic 1 indicates the upper byte (msb) and a logic 0 indicates the lower byte (lsb). the upper byte is transferred first. if a 16-bit data structure is used (db_sel = logic 0), this bit will always be logic 1 (note 1) pin no.
36 description i/o name i o db_sel cs 8 3 table 5. bus-65153 pin descriptions - continued dma handshake and transfer control (8) o o o i i o addr_ena dt_ack 7 2 hs_fail dt_grt 6 1 wrt dt_req 4 69 interface to 1553 pulse transformers (4) description i/o name pin no. channel a inverted 1553 serial data i/o tx/txa 44 channel b non-inverted 1553 serial data. channel b inverted 1553 serial data channel a non-inverted 1553 serial data i/o i/o i/o rx/txa 40 rx/txb 9 rx/txb 5 remote terminal address inputs. i 34 i i i rtadd03 33 rtadd02 description rt address (8) name i rtadd00 (lsb) 30 31 o i i rt_add_p 29 rt_add_lat 28 rt_add_err 27 rtadd01 31 data transfer request. active low level output signal used to inform the subsystem that the bus-65153 needs control of the data bus to perform a transfer. stays low until dt_grt is received and the transfer is completed or until a handshake failure timeout has occurred. data transfer grant. active low level input signal from the subsystem that, in response to a data transfer request, passes control of the parallel data bus to the bus-65153. data transfer acknowledge - active low level output signal used to inform the subsystem that the bus-65153 has received dt_grt in response to dt_req. dt_ack remains active until the transfer is complete. chip select - active low level output pulse present in the middle of every data transfer cycle. when the bus-65153 is writing data to the subsystem, this signal occurs when the data is valid and should be used to latch the data (rec- ommend using rising edge). when the bus-65153 is reading data from the subsystem, this signal is used to inform the subsystem when to drive the data bus. (note 1) read/write - output signal that controls the direction of the data transfers. the direction is normally outward (write = logic 0) and only turns inward (read = logic 1) when the first data word is needed from the subsystem. the output will return low (write) after the transmission of the last data word on the 1553 bus. (note 1) handshake failure - active low level output used to flag the subsystem that dt_grt was not received in response to dt_req in time to perform a data transfer. latched low and cleared by the next nbgrt or reset. address enable. active low level input signal used to control the operation of wrt, cs, and address bus a13 through a00. if a logic 0 is applied, the above signals are always active. if a logic 1 is applied, these signals are kept in their high impedance state except for when a data transfer is being performed (dt_ack = logic 0) data bus select - input signal used to select the data bus structure (8- or 16-bit width) logic 0 selects 16-bit data bus logic 1 selects 8-bit data bus note: for 8-bit data bus operation, d15 to d08 should be connected directly to d07 to d00, respectively. notes: 1. a13 through a0, cs, and wrt will be placed in a high impedance state if addr_ena is high and dtack is inactive (high). 2. the rt status word inputs illcmd, servreq, ssflag, and busy are sampled approximately 5 ms following the mid-parity bit zero crossing of the received command word. remote terminal address [4:0] - input signal of the address parity bit. the combination of rt_ad_[0:4], and rt_ad_p must comprise an odd parity sum in order to enable recognition of the terminal's address. remote terminal address latch. when low, the internal rdad4-0 and rtadp register tracks whatever is applied to the respective input pins. when rt_add_lat is high, the information that was on rtad4-0 and rtadp the last time that rt_add_lat was low is latched internally. the internal rtad4-0 and rtadp are cleared to logic 0 when reset is low. i/o remote terminal address parity error output signal that reflects the parity combination of the rt_ad_[4:0] inputs and rt_ad_p input. high level indicates odd parity, low level indicates even parity. note, if rt_add_err is low, then the bus-65153 will not recognize any valid command word directed to its own rt address. (table 5 continues on the next page.) pin no. rtadd04 (msb) pin no.
37 remote terminal failure - latched low level output that goes low if a loopback failure (or transmitter shutdown timeout) has occurred during a transmission cycle. a loopback failure occurs under any of the following conditions: (1) the first transmitted word (status word) contains an incorrect rt address field, (2) the received version of any transmitted word is either invalid or contains the incorrect sync type, (3) the received 16-bit data pattern for the last transmitted word does not match that of the transmitted version of the word and/or (4) a transmitter timeout (668 ms) has occurred. reset by the start of the next transmission cycle (status word) or a low level on the reset input. an rtfail condition (low level output on rtfail) will cause the terminal flag bit in the rt status register to be set. when this occurs, the rt flag status word bit will be set in response to the next valid nonbroadcast command. description i/o name pin no. i busy 68 table 5. bus-65153 pin descriptions - continued rt status word inputs (4) o i i ssflag 67 servreq 66 illcmd 65 o description i/o name pin no. o incmd 41 message timing output signals (5) o o o nbgrt 39 rtfail 38 gbr 37 me 42 factory test inputs (3) pin no. name i/o description connect to + 5 volts. connect to + 5 volts. connect to + 5 volts. i i i 48 47 46 notes: 1. a13 through a0, cs, and wrt will be placed in a high impedance state if addr_ena is high and dtack is inactive (high). 2. the rt status word inputs illcmd, servreq, ssflag, and busy are sampled approximately 5 ms following the mid-parity bit zero crossing of the received command word. illegal command input. active low input used to illegalize any command. if low when sampled, the message error bit (bit 10) in the status word will be set. the response to an illegal transmit command will be a status word only. the only effect of illegalizing a receive command will to inhibit gbr. an illegalized mode code will not perform the actual mode functions. (note 2) service request - input signal used to control the service request bit (bit 8) in the status word. if low when sam- pled, the service request bit will be set. if high, it will be logic0. (note 2) subsystem flag - input signal used to control the subsystem flag bit (bit 2) in the status word. if low when sam- pled, the subsystem flag bit will be set. if high, the subsystem flag bit will be logic 0. (note 2) input signal used to control the busy bit (bit 3) in the status word. if low when sampled, the busy bit will be set. if high, it will be cleared. note, if the busy bit is set and the command was a transmit command, only the status word would be transmitted. has no effect on data received following a receive command. (note 2) new bus grant - low level output pulse (2 clock cycles wide), that is used to indicate the start of a new protocol sequence in response to the command word just received from the 1553 bus. good block received - low level output pulse (2 clock cycles wide) that is used to flag the subsystem that a valid, legal, nonmode receive command with the correct number of data words has been received without a message error and successfully transferred to the subsystem in command - active low level output signal used to inform the subsystem that the bus-65153 is presently servic- ing a command that came in on the 1553 bus. message error - active low level output signal used to flag the subsystem that there was a message error on the 1553 bus communication (word, gap, or word count error). this output goes low upon detecting the error and is reset at the start of the next nbgrt pulse or master reset. if this output goes low, all further command servicing is aborted. factory test point factory test point factory test point
38 pin pin table 6. bus-65153/63 pin listing name name 36 1 dt_grt -15 (-12)volts 37 2 gbr dt_ack 38 3 rtfail cs 39 4 nbgrt wrt 40 5 rx/tx a rx/tx b 41 6 incmd hs_fail 42 7 43 8 clocksel db_sel 44 9 rx/tx a rx/tx b 45 10 46 11 factory test point db14 47 12 factory test point db13 48 13 factory test point db12 49 14 txinh db11 50 15 at3 db10 51 16 clock in db09 52 17 at2 db08 53 18 at11 (msb) gnd 54 19 a10 db07 55 20 a09 db06 56 21 a08 db05 57 22 a07 (lsb) db04 58 23 a06 db03 24 a05 (msb) db02 60 25 a04 db01 61 26 62 27 a02 rt_add_err 63 28 a01 (lsb) rt_add_lat 64 29 a00 rt_add_p 65 30 66 31 servreq rtadd01 67 32 ssflag rtadd02 68 33 busy rtadd03 69 34 dt_req rtadd04 (msb) 70 35 + 5 volts b + 5 va me addr_ena reset db!5 (msb) a03 db00 (lsb) illcmd rtadd00 (lsb) 1.000 max (25.4) 0.400 (10.16) 1.700 (43.18) index denotes pin 1 0.215 (5.46) max notes: 1. dimensions are in inches (millimeters). 2. package material: alumina (al 2 o 3 ). 3. lead material: kovar, plated by 150 m minimum nickel, plated by 50 m minimum gold. 1.900 max (48.26) 0.180 0.010 typ (4.57 0.25) 0.100 (2.54) 0.100 (2.54) typ 0.050 (1.27) typ 0.600 (15.24) 0.018 0.002 dia typ (0.46 0.05) 34 35 36 37 69 70 2 top view bottom view index denotes pin 1 1.900 (48.26) max side view 70 36 35 1 0.015 0.002 typ (0.381 0.051) 1.900 max (48.26) 34 eq sp @ 0.050 = 1.700 (43.18) (1.27) tol noncum 0.050 typ (1.27) 0.400 min typ (10.16) index denotes pin 1 1.000 max (25.4) 0.215 (5.46) max 0.010 0.002 typ (0.254 0.051) 0.070 0.010 (1.78) pin numbers for ref only top view side view notes: 1. dimensions are in inches (millimeters). 2. package material: alumina (al 2 o 3 ). 3. lead material: kovar, plated by 150 m minimum nickel, plated by 50 m minimum gold. figure 22. bus-65163/64 flat pack mechanical outline figure 21. bus-65153/54 dip mechanical outline 59
39 ordering information bus-651xx-xx0x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data power supply and packaging 53 = +5 v/-15 v dip 54 = +5 v/-12 v dip 63 = +5 v/-15 v flat pack 64 = +5 v/-12 v flat pack *standard ddc processing with burn-in and full temperature test see table below. also available as desc p/n 5962-92162-01hxc. data bus transformers: for bus-65153/63 use bus-25679, b-2203, lpb-5002, lpb-5009, or m21038/27-02. for bus-65154/64 use bus-29854, b-2204, lpb-5001, lpb-5008, or m21038/27-03. 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing
40 g-08/98-0 printed in the u.s.a. ilc data device corporation registered to iso 9001 file no. a5976 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7257 or 7381 headquarters - tel: (631) 567-5600 ext. 7257 or 7381, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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